As microelectronic devices get increasingly smaller, new problems with fabricating the devices appear. For example, microelectronic devices are typically fabricated by a process where different layers that provide specialized functions are deposited, patterned, and etched, and then subsequent layers are deposited over the top of the resultant structure, and the process continues in this manner for several layers until the microelectronic device is completed.
Because the different deposited layers are patterned and etched, the upper surface of the microelectronic device is made very uneven. This roughness of the upper surface of the microelectronic device is enhanced as each successive layer is deposited over a previously patterned layer, and then it too is patterned and overlaid with subsequent layers.
At a time when microelectronic devices occupied a relatively large surface area, this condition was not too much of a problem, as the various layers could be deposited to a thickness that was sufficient to overcome the size of the steps that were created during the patterning process. Alternately, the various structures could be formed at a distance from each other that was sufficiently far apart that the various steps of the structures did not interfere to too great an extent with each other.
However, as the surface area in which a microelectronic device is fabricated has been reduced, the steps caused by the successive layers have become more of a problem. One aspect of this problem is that it becomes increasingly difficult to adequately deposit successive layers within the deep crevices that tend to be formed between the successive patterned structures. Further, the rough topography of these resultant microelectronic devices tends to induce stress points within the layers, which tend to reduce the microelectronic device's resistance to failure in certain operating conditions and environments.
To counteract these problems, microelectronic devices are typically planarized to some extent and in some manner before successive layers are deposited on underlying layers. This is often accomplished with a process known as chemical mechanical polishing. In this process, the surface of the substrate on which the microelectronic devices are formed is abraded mechanically against a polishing pad, typically with the application of a slurry that also chemically erodes the surface of the substrate. This controlled chemical mechanical polishing tends to wear away those points on the upper surface of the substrate that are higher than other points, and thereby planarizes the microelectronic devices.
Unfortunately, chemical mechanical polishing tends to erode materials that are softer away from the surface of the substrate at a rate that is greater than the erosion of materials that are harder. As the surface of a microelectronic device typically has different structures of different materials exposed at the top surface at any given point during its fabrication, those structures that are formed of softer materials tend to erode at a rate that is greater than their neighboring structures that are formed of harder materials.
This difference in the rate of erosion of various structures at the surface of the microelectronic device tends to work against the general goal of planarizing the surface of the microelectronic device, because the softer structures tend to be eroded to a level that is below the level of the harder structures. This typically appears in a cross section as a cavity at the top surface of the softer structures between the laterally surrounding harder structures. This condition can also be described as a dishing of the softer structures between the laterally surrounding harder structures, because the erosion of the softer structures tends to be somewhat greater near the centers of the upper surfaces of the softer structures, and somewhat less near the edges of the upper surfaces of the softer structures where the laterally surrounding harder structures tend to offer some protection from various aspects of the chemical mechanical polishing process.
As a specific example, copper elements that are deposited on the surface of a microelectronic device tend to be softer than the laterally surrounding elements, such as oxide. After chemical mechanical polishing, the copper structures, such as lead lines, tend to be dished between the laterally surrounding oxide elements. Thus, at least two undesirable conditions are presented. First, the planarization is not optimal, because the surface of the copper structures tends to be below the surface of the laterally surrounding oxide elements. Second, the copper structures might no longer be deposited to the desired thickness.
What is needed, therefore, is a system for reducing the problems with chemical mechanical polishing as described above.